The present invention generally relates to the fabrication of metal conductive lines and vias that provide the interconnection of integrated circuits in semiconductor devices and/or the interconnections in a multi-layer substrate on which semiconductor device(s) are mounted and, more particularly, to the fabrication of conductive lines and vias by a process known as damascene.
In very and ultra large scale integration (VLSI and ULSI) circuits, an insulating or dielectric material, such as silicon oxide, of the semiconductor device in the dual damascene process is patterned with several thousand openings for the conductive lines and vias which are filled with metal, such as aluminum, and serve to interconnect the active and/or passive elements of the integrated circuit. The dual damascene process also is used for forming the multilevel conductive lines of metal, such as copper, in the insulating layers, such as polyimide, of multilayer substrates on which semiconductor devices are mounted.
Damascene is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in addition to forming the grooves of single damascene, conductive via openings also are formed. In the standard dual damascene process, the insulating layer is coated with a photoresist which is exposed through a first mask with an image pattern of the via openings and the pattern is anisotropically etched in the upper half of the insulating layer. The photoresist now is exposed through a second mask with an image pattern of the conductive lines openings, after being aligned with the first mask pattern to encompass the via openings. In anisotropically etching the openings for the conductive lines in the upper half of the insulating material, the via openings already present in the upper half are etched in the lower half of the insulating material. After the etching is complete, both the vias and the line openings are filled with metal. Dual damascene is an improvement over single damascene because it permits the filling of both the conductive grooves and vias with metal at the same time, thereby eliminating process steps.
Although this standard damascene offers advantages over other processes for forming interconnections, it has a number of disadvantages, such as it requires two masking steps to form the pattern first for the vias and subsequently for the conductive lines. These two masking steps require critical alignment to position the via within groove. It is highly desirable to have the length dimension of the via extend the full width dimension of the conductive line, but, because that would require more critical alignment of the two masks, the via length dimension is designed slightly smaller than the width dimension of the conductive line in the standard dual damascene process. Further, the edges of the via openings in the lower half of the insulating layer, after the second etching, are poorly defined because of the two etchings. Thus, improvements are needed in the standard damascene process to permit the via length to extend of full width of the conductive line without critical alignment of masks and to eliminate the poor edge definition of the via openings.